The computer industry, with the advances of silicon technology, is constantly faced with the complexities of Data Buses. The high speed of microprocessor CPU requires high speed of data bus between the memory subsystem and the front end CPU data bus. Speed without density of memory is an unbalanced combination. The CPU by itself cannot increase performance and it does not perform at the speed it was designed for. A bottleneck is created between memory and CPU Front End bus. With advances of Internet, complex application programs and operating systems, memory subsystems with high-density memory modules have become a necessity. However, as the density of memory goes up so does the capacitive loading of each data bit of the data bus. With the increase of the capacitive loading on the data bus, the driver of the data bit line is taxed for higher driving capability. As is well known, when the capacitive loading on the data line increases, for a given driver capability, the speed by which the driver circuit can change state on the data line is decreasing. The two are inversely proportional.
Many schemes have been designed with emphasis in speed and density. For that purpose, circuits utilizing FET switches have been designed into the data path to reduce the capacitive loading and thus allow for increase in data speed.
There are several factors to be considered in the design of such circuits:
1) Data pulse widths in the nanosecond and sub nanosecond range.
2) Data bus width to satisfy wide Data Bus requirements of the CPU.
3) High Memory density on the same Data Bus (More Memory Modules attached to the same Data Bus, more connectors on the motherboard attached to the Bus.)
4) Presence of physical parameters of Resistance, Inductance and capacitance in the structure of the Data Bus and on the devices (Connectors, Memory modules, Printed circuit boards, Memory chips and logic chips connected to the Bus).
5) Effects of the physical RLC quantities affecting the overall speed by which data can be transported on the Bus and thus the overall performance and bandwidth of such Bus.
6) Synchronization of the Data signals and strobe signals required to latch the data at the destination receiver.
An example of a prior art approach for such switching circuits utilizing FET switches is shown in FIG. 5a. This circuit represents the High Speed CMOS Bus Exchange Switch, model QS3388, manufactured by Quality Semiconductor, Inc. The circuit utilizes a number of FET switches, a typical FET switch being shown in FIG. 5b. 
Referring now to FIG. 5b, the FET switch is seen to have three terminals: the source 1, the drain 2, and the gate 5. When the FET switch is TRUE, the source and drain are in an ON state, that is, they are connected through a very low resistance, typically 5 ohms in the QS3388. A FALSE signal on the gate will cause the source to be essentially isolated from the drain, or at least, to present an extremely high resistance between the two, putting the FET switch into an OFF state. Most importantly, the transition between the ON and OFF states takes place in a fraction of a nanosecond.
The QS3388 is built upon a single silicon substrate, to maximize switching speed. It contains four sub-circuits, each of which contains an A port, a B port, a C port, and a D port. The A and B ports are intended for connection to A and B memory banks, while the C and D ports are intended for connection to C and D buses. Depending on the states of the control signals BX and BE, the C bus may be connected either to the A or the B bus, and the D bus may be connected to either of these two memory ports.
The Function Table or Truth Table, shown in FIG. 5c shows the various states of the circuits, dependent upon the states of the control signals.
The current invention, in comparison to the prior art, is a tri-directional high speed FET switch, implemented as an arrangement of FET switches built on the same silicon substrate to maximize speed and accurate control, and is intended for use with memory circuits. In its primary embodiment, this design provides eight sets of three ports each; a C port is intended for connection to the computer bus; an A port for connection to a bit of a first, or A memory bank; and a B port for connection to a bit of a second, or B memory bank.
Unlike the prior art, however, the present invention allows the bus not only to be connected to either the A or B memory bank; it also allows the A memory bank to be connected to the B memory bank, creating a xe2x80x9cthird statexe2x80x9d. It further produces a pair of strobe signals synchronized with the data signals on the A and B memory banks; and a pull-up and pull down signal, also synchronized with the data signals on the A and B memory banks.
The present invention, when used in a configuration described in U.S. patent Ser. No. 09/572,641, provides a significant improvement in memory access speed and accuracy, with substantial noise reduction over the prior art.
It is an object of the current invention to provide a microelectronic chip to act as a switching interface between a memory bank and the data bus of a computer memory system. It is a specific object to provide such a chip whose circuitry is implemented in accordance with an interleaved memory system architecture. It is a further specific object that said chip is implemented in accordance with a quad-speed memory architecture.
In accordance with a first aspect of the invention, a high-speed switching element includes a first port, Cn, a second port An, and a third port Bn, and wherein a first FET switch source is connected to Cn, a second FET switch source is connected to the first FET switch drain, and the drain of the second FET switch is connected to An, and a third FET switch source is also connected to the drain of the first FET switch, and the drain of the third FET switch is connected to Bn.
In accordance with a second aspect of the invention, a second high-speed switching element includes a first port DQS_CA, a second port DQS A, and a third port DQS_PU, a fourth port DQS_CB, a fifth port DQS B, and a sixth port DQS_PD. A fourth FET switch source is connected to DQS_CA, and a fifth, a sixth, and a seventh FET switch are included. The sources of the fifth, a sixth, and a seventh FET switches are connected together, and are connected to the drain of the fourth FET switch. Further, the drain of the fifth FET switch is connected to DQS_PU, the drain of the sixth FET switch is connected to DQS A, and the drain of the seventh FET switch is connected to DQS_PD. In addition, an eighth FET switch source is connected to DQS_CB, and a ninth, a tenth, and an eleventh FET switch are included, where the sources of the ninth, the tenth, and the eleventh FET switches are connected together, and are further connected to the drain of the eighth FET switch. Finally, the drain of the ninth FET switch is connected to DQS_PU, the drain of the tenth FET switch is connected to DQS B, and the drain of the eleventh FET switch is connected to DQS_PD.
In accordance with a third aspect of the invention, a high-speed, tri-directional switching circuit is made up of eight of the switching elements in accordance the first aspect of the invention, where the gates of the first FET switch of each switching element is connected to the gate of the first FET switch of every other switching element, where the gates of the second FET switch of each such switching element is connected to the gate of the second FET switch of every other switching element, and where the gates of the third FET switch of each switching element is connected to the gate of the third FET switch of every other switching element.
In accordance with a fourth aspect of the invention, the switching circuit contains logic circuitry operating on control signals ME, BE, such that when ME is TRUE and SB is FALSE, then: each C port is isolated from the rest of the circuit, each B port is connected to the corresponding A port, DQS_CA is isolated from the rest of the circuit, DQS_CB is isolated from the rest of the circuit, DQS A is isolated from the rest of the circuit, and DQS B is isolated from the rest of the circuit. When ME is TRUE and SB is TRUE, then each C port, each B port, the DQS_CA port, the DQS_CB port, the DQS A port and the DQS B port are all isolated from the rest of the circuit and when ME is FALSE and SB is FALSE, then each C port is connected to the corresponding A port, each B port is connected to the corresponding A port, and to the corresponding C port, DQS_CA is connected to the DQS A port, and DQS_CB is connected to the DQS B port. When ME is FALSE and SB is TRUE, and BE CLK is FALSE, then each C port is connected to the corresponding A port, each B port is isolated from the rest of the circuit, DQS_CA is connected to the DQS_PU port, DQS_CB is connected to the DQS_PD port, DQS A is isolated from the rest of the circuit, and DQS B is isolated from the rest of the circuit. When ME is FALSE and SB is TRUE, and BE CLK is TRUE, then:each C port is connected to the corresponding B port, each A port is isolated from the rest of the circuit, DQS_CA is connected to the DQS_PD port, DQS_CB is connected to the DQS_PU port, DQS A is isolated from the rest of the circuit, and DQS B is isolated from the rest of the circuit.
In accordance with a fifth aspect of the invention, the switching circuit is implemented by microelectronic techniques, and in the form of a single semiconductor chip.